Hardware Implementation of Prearranged Tables Based Modular Inversion

Abstract

The computational complexity of modular multiplication and division, which are the most important operations of some recent public-key cryptographic algorithms, has been a touchy issue for years. This complexity can be efficiently reduced by using prearranged table based on the binary extended GCD algorithm. However, the reduction can be fulfilled if we take into consideration of the hardware design of the modular inversion algorithm. This paper presents a hardware implementation of prearranged tables based modular inversion algorithm on FPGA technology. This algorithm is fast, less computational cost and less number of operations needed in hardware implementations. The multiple-precision arithmetic is replaced by single-precision to reduce the size of the hardware design. The numerical results show that the operation times of a single-precision is performed efficiently.