Abstract
The plan to design hardware real-time operating system based on FPGA is presented and the harden of the μC/OS-II is done, in order to resolve the problem that the real-time operating system kernel takes a lot of system resources and reduces the schedulability of application. The major function module of RTOS is composed of four parts the management of the event flag group (EFG), the semaphore management, the task management and the clock management. The task control block (TCB) is realized based on chip registers as well as the task scheduler and the semaphore management of hard-core are built by combinational circuits, both of them give full play to the potential of the multi-task parallelism. The hardware system is described by VHDL, simulated through the ISE 8.2 and realized on FPGA. Simulation results show that the hardware realization of the system reduces the running time efficiently and makes it possible to apply in time-critical systems.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
