Abstract
This work describes the VHDL design and implementation of block-based motion estimation in order to make it feasible for real-time video applications. The design was functionally tested and simulated using ModelSim from Mentor Graphics tools, and then verified using both a VHDL testbench and the Matlab® Image processing tools. The design was tested for different image sizes at different clock frequencies with varying block sizes and search areas. With a clock frequency of 400 MHz, the estimated time for motion estimation for QCIF and CIF sequences shows the feasibility for real-time video-codec.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
