Hardware implementation of antenna array system for maximum SLL reduction

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Side lobe level (SLL) reduction has a great importance in recent communication systems. It is considered as one of the most important applications of digital beamforming since it reduces the effect of interference arriving outside the main lobe. This interference reduction increases the capacity of the communication systems. In this paper, the hardware implementation of an antenna array system for SLL reduction is introduced using microstrip technology. The proposed antenna array system consists of two main parts, the antenna array, and its feeding network. Power dividers play a vital role in various radio frequency and communication applications. A power divider can be utilized as a feeding network of an antenna array. For the synthesis of a radiation pattern, an unequal-split power divider is required. A new design for a four ports unequal circular sector power divider and its application to antenna array SLL reduction is introduced. The amplitude and phase of the signals emerging from each power divider branch are adjusted using stub and inset matching techniques. These matching techniques are used to adjust the branches impedances according to the desired power ratio. The design of the antenna array and the power divider are made using the software package CST MICROWAVE STUDIO. The power divider is realized on Rogers R03010 substrate with dielectric constant εr=10.2, loss tangent of 0.0035, and height h=1.28mm. In addition, a design for ultra-wide band (UWB) antenna element and array are introduced. The antenna elements and the array are realized on the FR4 (lossy) substrate with dielectric constant εr=4.5, loss tangent of 0.025, and height h=1.5mm. The fabrication is done using thin film technology and photolithographic technique. The experimental measurements are done using the vector network analyzer (VNA HP8719Es). Good agreement is found between the measurements and the simulation results.