Hardware Implementation of an Event-Based Message Passing Graphical Model Network

Abstract

This paper presents a hardware system that implements a factor graph, where messages are sent using an event-based belief propagation algorithm. The system, comprising an FPGA and an application specific integrated circuit (ASIC) chip, can be used to construct a graph with upto 16 output message channels. The ASIC chip with 16 channels is fabricated in a 0.35 um 2P4M CMOS process and occupies $2.16 \times 2.74$ mm2. Each channel dissipates 46 uW. The output analog messages of the channels are encoded through the interspike intervals of the output spike streams or events. The system can be used to implement graphs with arbitrary variable distributions for its inputs and using constraint functions, such as “plus” and “equality”. Using Kullback–Leibler divergence, we show that the measured distributions from the implemented graphs on the hardware show close similarity to the theoretical distributions.