Hardware Implementation of an Efficient Internet Protocol Routing Filter Design

Abstract

In this paper we propose a new mechanism for an efficient router design with focus to an IP address lookup algorithm, which uses a small amount of memory. Typically each filter is a destination address prefix and longest prefix matching is used to determine the next hop for each incoming packets. By exploiting the low memory access latency and high bandwidth of on chip memory high speed packet forwarding can be achieved using this data structure. When designing a router, three pertinent issues are to be addressed (i.e., routing lookup, switching and scheduling). The main objective of this paper is to design an efficient router that uses a fast routing lookup algorithm and an efficient data compression algorithm to store the routing table in a tree, which uses a very little memory in the router. The route lookup mechanism proposed in this paper, when implemented in a pipeline fashion in hardware, can achieve one route lookup for every memory access. With the current 50ns DRAM, this corresponds to approx 20×106 packets (lookups) per second. Analysis shows that this algorithm needs only 400kb memory for storing 20k entries thus achieving a high compression. This design can be easily scaled up from Internet protocol version 4 (Ipv4) to Internet protocol version 6 (IPv6).