Abstract
Automatic color equalization (ACE) algorithm is an effective method for color image enhancement, but its computational complexity is extremely high. In this paper, we first modify the ACE algorithm to reduce the computational complexity and realization cost while maintaining good visual quality. Subsequently, an efficient VLSI architecture for the hardware-friendly ACE algorithm is proposed to meet the requirement of real-time image enhancement. FPGA (Field Programmable Gate Arrays) implementation result shows that the proposed architecture can operate at 120MHz and achieve a throughput of 60 frame/s for 256×256 resolution images using about 1.15k and 1.78k of FPGA's logic (LUT) and register resources, respectively. Compared with the existing design, the proposed architecture can achieve higher performance with fewer hardware resources and comparable visual quality.
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