Hardware Implementation of A New Symmetric Multilevel Inverter Structure with less Number of Power Switches

Abstract

Multilevel inverters operate by synthesizing a desired voltage level in the output by using several DC sources in the input. Increasing the number of levels in the output leads to smaller output voltage steps, lower dv/dt, lower di/dt, less stress on the power devices, lower switching losses and less total harmonic distortion. With these characteristics, multilevel inverters are suitable in high power and high voltage applications. The main problem of multilevel inverters however is the high power switches count requirement. This paper proposes a new symmetric multi-level inverter structure with reduced number of power switches which in turn reduces the control complexity. It is capable of providing the desired output voltage levels, which in this paper an output of nine levels is considered but can be simply extended to higher levels depending on the application. A modified Pulse Width Modulation (PWM) control method with less number of carrier signals is also introduced for the new multilevel inverter structure. The performance of the proposed nine-level as established through simulation and experimental study is found to be in accordance to the theoretical perspective.