Abstract
Unum type-II based Sets-Of-Real-Numbers (SORN) arithmetic is a recently proposed, promising number representation providing fast and low complex implementations of arithmetic operations at the expense of low resolution. The format can be applied for constraining large optimization problems by means of preprocessing. In this work SORN arithmetic is applied for reducing the latency of a Sphere Decoder by excluding a number of solutions in advance. In particular, a comprehensive hardware implementation is presented, consisting of an adapted Sphere Decoder, as well as SORN and matrix preprocessing. Logic and physical synthesis evaluations show that the mean number of visited nodes within the Sphere Decoder can be reduced by up to 76%, resulting in an overall latency reduction of up to 20%. This improvement comes with an area and energy increase of up to 58% and 83%, respectively, compared to a standard Schnorr-Euchner Sphere Decoder.
Highlights
AND RELATED WORKT HE representation of numbers in digital systems and their manipulation in terms of arithmetic operations is still a paramount challenge for the design of modern highperformance digital circuits and systems [1]
Sphere Decoding for wireless MIMO communication can be accelerated by introducing SORN-based preprocessing which deletes nodes from the Sphere Decoder (SD) search tree and effectively reduces the latency by means of visited nodes
For the presented evaluation the mean number of visited nodes within the adapted SD can be significantly reduced by up to 76% for negative signal-to-noise ratio (SNR), compared to a SotA SchnorrEuchner SD (SE-SD)
Summary
T HE representation of numbers in digital systems and their manipulation in terms of arithmetic operations is still a paramount challenge for the design of modern highperformance digital circuits and systems [1]. Arithmetic operations are mapped to lookup tables (LUTs) which are highly appropriate for hardware implementation. This kind of arithmetic is especially well suited for constraining large optimization problems by means of preprocessing for example when solving linear or nonlinear systems of equations [8]. A possible target application for such kind of arithmetic is the symbol detection at the receiver in a Multiple-InputMultiple-Output (MIMO) wireless communication system, where a finite-alphabet-constrained least-squares problem has to be solved in order to reconstruct the transmitted data [9]. The presented SORN preprocessing unit reduces the number of possible solutions for the MIMO detection problem in order to simplify SotA detectors. Demonstration of the suitability of SORN arithmetic for signal processing architectures, in this work applied to a SD for MIMO symbol detection. A comprehensive evaluation of the proposed approach, based on software- and hardware-related register-transferlevel (RTL) simulations, as well as CMOS 28 nm syntheses, including comparisons with a conventional SchnorrEuchner SD (SE-SD) implementation and other literature SD and comparable SotA algorithms and implementations
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