Hardware-friendly HEVC motion estimation: new algorithms and efficient VLSI designs targeting high definition videos

Abstract

In this article the spread and iterative search (S&IS) and the low density and iterative search (LD&IS) motion estimation algorithms are presented. The proposed algorithms are hardware-friendly because they have a regular number of cycles to encode a block, they have a regular memory access and the parallelism can be better explored when compared to other published solutions. The proposed algorithms were evaluated under the high efficiency video coding reference software and compared with the state-of-art enhanced predictive zonal search (EPZS) algorithm and with the well know diamond search (DS) algorithm. The designed algorithms presented better BD-rate results than DS but they presented some losses when compared to EPZS. Since EPZS is not focused in a hardware design, it presents a lot of data dependencies, a irregular memory access, a non-deterministic number of operations to encode a block and it must store motion vectors of previously encoded frames. All these features are undesirable for many applications, including those ones focused on battery powered devices. To show the efficiency of the proposed algorithms, two architectures were designed targeting these algorithms and they were synthesized for Altera Stratix 4 and for ASIC using TSMC 90 nm standard-cells technology. Synthesis results show that the architectures are capable to process HD 1080p videos, at real time, by obtaining good results in terms of hardware resources use, power consumption and processing rate when compared to related works. The ASIC implementations are able to guarantee real-time performance for high definition videos consuming 12.5 and 13.5 mW, respectively. These results are possible because S&IS and LD&IS were developed focusing on hardware design.