Hardware‐efficient phase‐detection technique for digital clock and data recovery

Abstract

A phase-detection technique for digital clock and data recovery (CDR) in multi-Gbit/s serial links is presented. Compared to conventional sampling-based receivers, hardware efficiency at the system-level is achieved by extracting timing information from analysing the occurrence of certain patterns at the output of four comparators. The arrangement of the decision threshold and sampling time of these comparators is discussed, and the phase and frequency detection characteristic of such an arrangement is evaluated. The technique is validated through a proof-of-concept 12.5 Gbit/s CDR chip that is fabricated in 90nm CMOS.