Abstract
3D integrated circuits (3D ICs) based on through- silicon vias (TSVs) are widely used as a solution to solve the interconnect and power problems in IC design. However, as the structures of 3D ICs become more complex, testing has emerged as an important challenge. It is difficult to test power and ground TSVs because they are connected to a grid after stacking. In this paper, a built-in self-test architecture for power and ground TSVs is proposed. This architecture tests for three types of TSV faults that are critical to the operation of TSVs. The proposed test architecture can improve the reliability of 3D stacked IC by providing a suitable test for power and ground TSVs with little hardware overhead.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
