Hardware-efficient and accurately frequency offset compensation based on feedback structure and polar coordinates processing

Abstract

Compared with off-line digital signal processing (DSP) verification, achieving the expected performance and hardware efficiency in application specific integrated circuit (ASIC) is more critical for DSP to reduce power consumption and cost. The performance of traditional frequency offset compensation algorithms based on feedforward structure is strongly dependent on the accuracy of frequency offset estimation. Therefore, frequency offset calculation and loop filtering implemented in ASIC or field programmable gate array (FPGA) usually choose high word-width fixed-point or floating-point operations, which increase the consumption of logical resources and reduce the clock frequency that hardware logic can achieve. This work proposes a frequency offset compensation scheme based on polar coordinate processing and feedback structure, and a pre-decision-based angle differential estimator is used to estimate the residual frequency offset. In the proposed feedback structure, the frequency offset estimator is realized by a simple accumulator, and the input of the accumulator is the residual frequency offset or its scaling, which will reduce the requirement for the accuracy of the residual frequency offset estimator. The offline verification results show that the performance of the proposed algorithm is close to that of the traditional algorithm, but the proposed algorithm has lower logic resource consumption and higher clock frequency in hardware implementation based on FPGA. The performance of the proposed method is evaluated in real-time through 10-Gbps data rate polarization-multiplexed quadrature phase shift keying modulation after 20-km standard single-mode fiber transmission. Compared with offline processing in MATLAB®, no hardware implementation penalty is observed.