Hardware Design of Feature Point Extraction using SIFT algorithm

Abstract

In this paper, we design hardware architecture to accelerate feature point extraction using SIFT(Scale Invariant Feature Transform) algorithm for real-time embedded applications. The process of SIFT needs excessive amount of computations and memory accesses. To solve this problem, changing computation order and FIFO buffer are adopted. As a result, this hardware can extract feature points on qVGA(320x240) image in real-time. The proposed hardware is implemented in FPGA.