Hardware design of fast HEVC 2-D IDCT targeting real-time UHD 4K applications

Abstract

This paper presented a hardware design of an 4-points IDCT inverse transform module defined in the newest video coding standard, the HEVC. This work proposes a simpler way to calculate the HEVC 4-points IDCT. This approach focuses in the occurrence of special cases where the result can be calculated without the full IDCT processing. These simplifications reduced about 87.5% the number of 1-D IDCT calculations in the whole 2-D IDCT process, with an increasing of 0.4% in BD-Rate. The focus of the developed hardware design is to achieve real-time processing for UHD 4K (3840×2160 pixels) video sequences, with low hardware resources use and high performance. The architecture was implemented targeting a Cyclone V FPGA device. Synthesis results show that the designed hardware is capable to process UHD 4K videos in real time, processing up to 100 UHD 4K frames per second. Moreover, compared to the IDCT hardware design, without the proposed approach, the reduction in terms of hardware resources consumption achieves 72.3%.