Hardware Demonstrator of a Level-1 Track Finding Algorithm with FPGAs for the Phase II CMS Experiment

D Cieri

doi:10.1088/1742-6596/762/1/012020

Abstract

At the HL-LHC, proton bunches collide every 25 ns, producing an average of 140 pp interactions per bunch crossing. To operate in such an environment, the CMS experiment will need a Level-1 (L1) hardware trigger, able to identify interesting events within a latency of 12.5 μs. This novel L1 trigger will make use of data coming from the silicon tracker to constrain the trigger rate. Goal of this new track trigger will be to build L1 tracks from the tracker information.The architecture that will be implemented in future to process tracker data is still under discussion. One possibility is to adopt a system entirely based on FPGA electronic.The proposed track finding algorithm is based on the Hough transform method. The algorithm has been tested using simulated pp collision data and it is currently being demonstrated in hardware, using the “MP7”, which is a μTCA board with a powerful FPGA capable of handling data rates approaching 1 Tb/s.Two different implementations of the Hough transform technique are currently under investigation: one utilizes a systolic array to represent the Hough space, while the other exploits a pipelined approach.

Highlights

At the HL-LHC, proton bunches collide every 25 ns, producing an average of 140 pp interactions per bunch crossing. To operate in such an environment, the CMS experiment will need a Level-1 (L1) hardware trigger, able to identify interesting events within a latency of 12.5 μs. This novel L1 trigger will make use of data coming from the silicon tracker to constrain the trigger rate
The algorithm has been tested using simulated pp collision data and it is currently being demonstrated in hardware, using the “MP7”, which is a μTCA board with a powerful FPGA capable of handling data rates approaching 1 Tb/s
The High Luminosity (HL–LHC) upgrade [1] to the Large Hadron Collider will operate at an increased instantaneous luminosity, up to 7 times the nominal value, in order to collect an integrated luminosity of 3000 fb−1 in the decade following 2025

Summary

Introduction

The High Luminosity (HL–LHC) upgrade [1] to the Large Hadron Collider will operate at an increased instantaneous luminosity, up to 7 times the nominal value, in order to collect an integrated luminosity of 3000 fb−1 in the decade following 2025. Before transmitting tracking information to the trigger processors, the amount of data needs to be reduced This will be achieved through an on-detector selection on transverse momentum of particles pT. 2. The Time Multiplexed Track Trigger The fundamental idea of a Time Multiplexed Trigger (TMT) [6] is that all data from a single event flow to a single destination (node) for processing. The Time Multiplexed Track Trigger The fundamental idea of a Time Multiplexed Trigger (TMT) [6] is that all data from a single event flow to a single destination (node) for processing This requires two processing layers with a passive switching network between them, the Pre-Processor (PP) and the Main-Processor (MP). Each MP will have a period of time (Time Multiplexed period ) proportional to the total number of MP boards to run the algorithm This particular system is well matched to FPGA processing. Our choice ended up being the μTCA board MP7 [7], originally designed for the CMS L1 calorimeter trigger upgrade, which contains a powerful Virtex 7 FPGA with 72 I/O optical links (total bandwidth ∼ 1 Tb/s)

L1 Track Finding with Hough Transform

Conclusions