Abstract

The proposal of the ubiquitous power Internet of Things (UPIoT) has increased the demand for communication coverage and data collection of smart grid; the quantity and quality of communication networks are facing greater challenges. This brief applies (73, 37, 13) quadratic residue (QR) codes to power line carrier technology to improve the quality of local data communication in UPIoT. In order to improve the decoding performance of the QR codes, an induction method for the error pattern is proposed, which can divide the originally coupled error pattern into six parts and reuse the same module for decoding. This method greatly reduces the resource requirements, so that (73, 37, 13) QR code can be implemented on FPGA hardware. Notably, the hardware architecture is a modular framework, which can fit into an FPGA with different sizes. As an example (73, 37, 13), QR code is implemented on Intel Arria10 FPGA; the experimental result shows that the maximum decoding frequency of this architecture is 21.7 M Hz, which achieves 4121x speedup compared to CPU. Moreover, the proposed architecture benefits from high flexibility, such as modular design and decoding framework in the form of the pipeline which can be seen as an alternative scheme for decoding long‐length QR codes.

Highlights

  • With the development of power systems, the types and quantities of electrical equipment are increasing rapidly, for example, Energy Storage (ES) is being widely adopted in the grid to meet the needs of intermittent power generation [1]

  • The “Ubiquitous” of Ubiquitous power Internet of Things (UPIoT) is embodied in the various nodes of the power system, that means the real-time interconnection of people, machinery, power networks, and platforms can be achieved at any time [4]

  • There is no doubt that the more errors an encoded message has, the longer decoding time cost, and the unstable decoding delay will have an impact on the real-time performance of the IOT device

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Summary

Introduction

With the development of power systems, the types and quantities of electrical equipment are increasing rapidly, for example, Energy Storage (ES) is being widely adopted in the grid to meet the needs of intermittent power generation [1]. The types and quantities of data measured by local sensors in UPIoT will increase greatly with the development of power networks. The good characteristics of PLC, such as direct application of power line transmission data, no need to modify the wiring layout, easy implementation, and two-way communication, can meet the basic characteristics of the local transmission network. Most of the transmitted signals between the sensors and the IoT gateway are expected to be power status data and control signals, which can be regard as short data; the advantages of Low-Density Parity Check (LDPC) codes cannot reflect due to the dense and short communication data [8]. We propose to use quadratic residue (QR) codes [13] to encode data and control signals in front of the PLC channel, and still can use more commonly used modulation methods such as OFDM; it can obtain the following advantages:. We implemented the hardware decoding architecture of (73, 37, 13) QR code on the Intel Arria10 10AX115-U4F45I1SG FPGA platform, achieving a maximum clock frequency (fmax) of 260.42 MHz, which is equivalent to 21.7 MHz decoding frequency

QR Code and Decoding Algorithm
Error Pattern Induction Method
Hardware Architecture Design
Result
Conclusion
Full Text
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