Hardware Constructions for Error Detection in Lightweight Authenticated Cipher ASCON Benchmarked on FPGA

Abstract

Lightweight cryptography plays a vital role in securing resource-constrained embedded systems such as deeply-embedded systems, RFID tags, sensor networks, and the Internet of nano-Things. ASCON is one of the finalists for the National Institute of Standards and Technology (NIST) lightweight cryptography standardization competition advanced to the final round in April 2021. It is designed to provide authenticated encryption with associated data (AEAD) and hashing functionalities in hardware and software implementations. ASCON’s lightweight design utilizes a 320-bit permutation, bit-sliced into five 64-bit register words, providing 128-bit level security. This brief, for the first time, proposes error detection mechanisms for secure hardware implementations of ASCON. The proposed schemes, i.e., signature, interleaved signature, and cyclic redundancy check approaches are presented for both LUT and logic-based implementations of ASCON. The proposed error detection schemes are also benchmarked on two FPGA families (Spartan-7 and Kintex-7), achieving acceptable area, power, and delay overheads. The proposed mechanisms also provide a high error coverage (99.99%) shown via simulations performed for 640,000 injected faults. Hence, these approaches aim to make the respective ASCON architectures more reliable.