Hardware Architecture for Real-time License Plate Location on FPGA

Abstract

Automatic license plate location (LPL) plays a significant role in intelligent transportation systems. In this paper, a high performance real-time LPL system is implemented on a field programmable gate array (FPGA) hardware. A high location rate could be achieved even if the background scenes are complicated. A memory based array computing pipeline architecture and a muti channel SRAM architecture are proposed to take full advantage of the parallel processing ability of FPGA, reduce the consumption of logic elements (LEs), and accelerate the LPL process. A 6 stages pipeline architecture is designed to make the LPL system meet real-time requirement and achieve optimal parallelism. The LPL system is tested with 1549 images taken from different places and conditions, the test images contain vehicles with Chinese license plates. The resolution of the test images is 720×576, the corresponding LPL speed is 30.9 ms. The location rate of this LPL system is 92.4%, and the FPGA resource consumption is 15 324 LEs.