Hardware architecture for optical flow estimation in real time

Abstract

Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. A specific architecture for this task has been developed and tested with simulators of hardware description languages. This architecture can estimate the optical flow in real time and can be constructed with FPGA or ASIC devices. This hardware may have many applications in fields like object recognition, image segmentation, autonomous navigation and security systems. To simulate image processing models described in VHDL an application specific test bench has been designed.