Hardware and Software Solutions to Increase the Reliability of Combinational Logic in the FPGA Basis

Abstract

This article proposes software and hardware solutions to increase the fault tolerance of combinational circuits in the basis of programmable logic integrated circuits (PLD), which can also be used for user-programmable gate arrays (FPGAs). For this, a software solution is implemented that searches for critical logic elements, an error in which will most likely affect the project outputs in the FPGA basis. An effective method for calculating the sensitivity coefficient of combinational logic in the FPGA basis is proposed. The method for evaluating the fault tolerance of combinational circuits in the FPGA basis is described in detail, and the choice of the sensitivity coefficient of the circuit to single errors as the base technology-independent metric of the fault tolerance of combinational circuits in the FPGA basis is justified.Variants of minimizing the built-in redundancy are proposed.Experimental work was carried out on the formation of fault-tolerant designs of combinational circuits in the basis of fault-tolerant FPGAs.