Hardware accelerators for pairing based cryptosystems

Abstract

Polynomial basis hardware architectures are described for the mathematical operations required in pairing based cryptosystems in characteristic p = 3. In hardware, arithmetic operations in extension fields of GF(3m) can be parallelised, and this results in high performance dedicated processors for efficient Tate pairing calculation. The implementation aspects of two such hardware processors are discussed through prototyping over GF(397) on the Xilinx Virtex2 and Virtex2Pro FPGA technologies.