Hardware Accelerator Design of Non-linear Optimization Correlative Scan Matching Algorithm in 2D LiDAR SLAM for Mobile Robots

Abstract

When building a map of surroundings and inferring the location based on the map, simultaneous localization and mapping (SLAM) is the main solution based on sensor data. Correlative Scan Matching (CSM) is used for scan matching to localize the robot according to the environmental information in SLAM. This paper presents a hardware accelerator design of NLO-CSM (Non-linear Optimization CSM) for scan matching utilized in 2D LiDAR SLAM. Pipeline processing and module reusing schemes are utilized in the proposed NLO-CSM algorithm hardware accelerator to achieve fast compute, high energy and area efficiency, while ensuring high calculation accuracy. Based on Xilinx's Zynq-7020 FPGA device, the FPGA implementation results show that at 100 MHz clock, the proposed hardware accelerator achieves a scan matching at 8.98 ms and 7.15 mJ per frame, and the power consumption is 0.79 W. The proposed design outperforms the ARM-A9 dual-core CPU implementation with 92.74% increase in computing speed and 90.71% saving in energy consumption. Furthermore, the ASIC implementation in 65-nm CMOS process reduces the computing time to 5.94 ms and energy consumption to 0.06 mJ per frame.