Hardware accelerated simulation tool (HAST)

Abstract

Most simulations of communications systems are done using a high-level language such as Matlab or C. As the complexity of these simulations grows and higher performance is expected, the runtime of the simulations becomes unacceptable. A promising solution to this problem is to move frequently executed (bottleneck) sections of the simulation into dedicated hardware that is implemented on field-programmable gate arrays (FPGAs). An FPGA, coupled with a very high-speed interface to the PC, is an ideal platform for such an accelerator. The system described in this paper is based on a PCI board with multiple Xilinx FPGAs. A typical wireless communications channel can be described as a finite impulse response (FIR) filter with time-varying coefficients. In this paper a FIR filter is implemented using dedicated hardware mapped onto a Xilinx FPGA board. The filter has additional hardware that interpolates between adjacent coefficients for more continuous and realistic results. The same filter is created in optimized Matlab for software simulation. Another common algorithm implemented in modern communication systems is a fast Fourier transform (FFT). This paper compares the software simulation and co-simulation approaches for both the FIR and the FFT blocks. Dramatic improvements in overall simulation throughput are demonstrated by using the hardware accelerator, as opposed to a pure software simulation