HALT evaluation of SJ BIST technology for electronic prognostics

Abstract

This paper presents the design, test, and results of a highly accelerated life test (HALT) evaluation of a soft-core called Solder Joint Built-in Self-Test™ (SJ BIST™), a method for detecting faults caused by solder-joint fractures in monitored input/output (I/O) pins of field programmable gate array (FPGA) devices, especially those in ball grid array (BGA) type of packages. Modern electronics utilize large FPGAs packages attached to electronic boards by means of solder joints, such as solder balls, between the package and the board. Thermo-mechanical stresses — primarily heat and vibration — cause fatigue damage and eventual fracture failure of one or more balls, which causes intermittent operational faults leading to catastrophic failures in critical systems. Such intermittent faults are difficult to reproduce on a test bench and many field returns of electronic modules with intermittently failing solder balls are diagnosed with code no trouble found/could not reproduce. The SJ BIST soft-core offers a solution because it detects faults in monitored pins caused by fractured solder joints of programmed FPGAs on deployed electronic boards. At the end of the three-month HALT, selected FPGAs were subjected to die-and-pry and cross-section examination and comparison to the collected data. Analysis confirmed that SJ BIST did report the occurrence of faults on damaged pins, and SJ BIST did not report any false negatives. The HALT confirmed the efficacy, accuracy, and reliability of SJ BIST as both a prognostic and diagnostic tool for FPGAs in BGA type of packages.