Abstract
To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class computing unit. This paper focuses on the Hardware Kernel and mainly its microcode control unit, which will leverage the elasticity to naturally evolve with Linux OS through key differentiating capabilities of field programmable gate arrays (FPGAs) when compared to the state of the art. To comply with the evolutive nature of Linux OS, or any Hardware Task incremental features, the proposed model generates page-faults signaling runtime errors that are handled at the kernel level as part of the virtual file system runtime. To evaluate the accelerator model’s programmability and its performance, a client-side application based on the AES 128-bit algorithm was implemented. Experiments demonstrate a flexible design approach in terms of hardware and software reconfiguration and significant performance increases consistent with rising processing demands or clock design frequencies.
Highlights
Since today’s most frequent demands for embedded devices are still grounded to performance, several operating systems for field programmable gate arrays (FPGAs) have been proposed to tackle the real-time performance issue of the CPU-only computing system, mainly through FPGA’s reconfigurability and high energy efficiency
The development process is carried out through the following steps: (1) writing a new application or refactoring an existing application according to a class Task concept; (2) running a parallelization tuning cycle using profilers to identify critical Linux kernel- and user-level subsystems that should be tuned for scalability; (3) running a co-simulation stage by applying the accelerator to the selected offload task candidates, through the integration of high-level synthesis tools such as Vivado HLS or MATLAB, to translate C/C++ programming models to appropriated register-transfer-level (RTL) representation; and (4) supporting the system designer in the creation of the full platform solutions, including board support package (BSP), stripped bare minimal Linux Operating System (OS), device drivers, middleware and applications software
This paper extends the notion of deep semantic integration of hardware accelerators into an operating system environment proposed by ReconOS [2], by introducing the parametrizable Hardware Kernel unit into the HAL-application-specific operating system (ASOS) accelerator model, to promote an evolutive elasticity beyond the Dynamic Partial Reconfiguration (DPR)-enabled one
Summary
Since today’s most frequent demands for embedded devices are still grounded to performance, several operating systems for FPGA have been proposed to tackle the real-time performance issue of the CPU-only computing system, mainly through FPGA’s reconfigurability and high energy efficiency. It provides the designer with a complete solution for developing reconfigurable systems that benefit from the synergy among software, hardware, and services, as well as deliver powerful computation solutions that can be built with just the right and needed resources. The HAL-ASOS accelerator framework is evaluated in Section 3, taking AES algorithm acceleration as a case study, and Section 4 concludes the paper
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