Guidelines for Area Ratio between Metal Lines and Vias to Improve the Reliability of Interconnect Systems in High-Density Electronic Devices

Abstract

This research was conducted in the context of the semiconductor market, with a demand for high-performance and highly integrated semiconductor systems that simultaneously enhance performance and reduce chip size. Scaling down the metal line and via in back-end-of-line (BEOL) structures is essential to efficiently deliver power to scaling down devices. This study utilized the finite element method (FEM) simulation technique to model the heat and current distribution for enhancing the efficiency of scaled-down structures. Due to current flow bottlenecks, an increase in the area ratio of the via to metal line (as the via becomes relatively smaller) leads to a temperature rise due to Joule heating. This trend follows a second-degree polynomial form, and the point where the temperature doubles compared to when the area ratio is one is situated at an area ratio of three. The temperature increase caused by Joule heating ultimately leads to destruction of the via, which directly affects the reliability of the BEOL structure. These experimental results can provide guidelines for designing with reliability considerations in mind, particularly in today’s semiconductor systems where significant scaling down is required in interconnect structures. They can also be widely applied to research aimed at developing interconnect structures that enhance reliability.