Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC)

Abstract

IT is with great pleasure that we introduce the special section on Design and Test of Systems-on-Chips (SoC) to the readership of the IEEE Transactions on Computers. This special section consists of eight papers that have been selected to cover a wide spectrum of techniques and applications which are encountered in the design, manufacturing, assembly, and test of today’s SoC. These papers are authored by outstanding researchers and cover experimental and speculative topics. As with all special sections, these topics are only representative of the publically available literature currently provided by the technical community. Systems-on-a-Chip (SoC) represent a rapidly growing and promising field in the electronic and computer industry. Such tremendous growth is the result of significant advances in microelectronic technology that make it possible to build on the same silicon substrate complex systems, including electronic (analog, digital, and mixed mode), mechanical, optical, RF, and microwave cores, as well as sensors, actuators, and software-based systems. As a result, SoCs are very complex hardware/software systems, offering high-performance features. Examples of possible applications include wireless systems, real-time control systems, space exploration systems, and others. SoCs offer the inherent advantages in which computers and their digital domain can be merged to a variety of technologies and applications which, in the past, were attained at boardlevel. The design and test of such complex systems, however, still constitutes a major challenge. From a design point of view, the ability to have a correctly functioning SOC depends on the ability to design and analyze a mixed-technology and to properly account for the interactions among the various cores. Proper management of interfaces between diverse cores and synchronization are examples of the problems to be faced. The unavailability of proper design and simulation tools for such complex systems and the limited resources for different technologies (such as mixed-signal systems) make such an effort rather difficult. The relation between the different modules of an SoC must be properly established using advanced techniques whose technological basis is just emerging. It is expected that these techniques will be highly inter and intradisciplinary in nature, thus involving designers with different backgrounds. Configurability and programmability of the cores in an SoC suggest that wide applicability of these systems is indeed possible with great flexibility in integration. A further issue that designers are confronting is the evaluation of different configurations associated with the high density integration of cores. The merging of different technologies (such as digital and analog) on a single chip is also of high speculative interest because the manufacturing and organization of these systems is in its infancy. These new features must be evaluated at the early design stages because they have a considerable effect on the performance of SoCs as well as their viability for cost-effective implementation. From a testing point of view, the development of proper test access mechanisms is one of the major challenges to be faced in the near future, as indicated also by the 1999 International Technology Roadmap for Semiconductors. The test access mechanisms must be compatible with the IEEE P1500 standard, which was developed for embedded core testing and which leaves the problem of the Test Access Mechanism (TAM) design to the system integrator. Several test access mechanisms have been proposed, including dedicated test bus, multiplexed access, etc., but the goal is to find a solution allowing the best trade-off between the test quality and cost (including the testing time). To evaluate test quality, however, complex failure mechanisms which might occur in such complex systems should also be evaluated. As an example, the possible occurrence of undesired coupling, noise, and skews between clock signals of diverse cores are some of the simplest failures which may affect the operation of the interfaces among the cores. Proper models, fault simulation tools, and test quality figures are needed. Testing time should also be reduced. In fact, while the design and test of SoCs requires a long time (similar to any computer system), the time-to-market of an SoC should be kept as short as possible to meet today’s consumers’ changing requirements. The high performance possibly offered by the integration of complex systems on the same chip makes SoCs very promising for real-time applications, like control systems for automotive, avionic, space, chemical plants, etc. As an example, the first prototypes of SOCs, including electronic and mechanical cores, have already been employed by NASA for space exploration missions. Such a promising application potential, however, poses the problem of reliable design and verification as well as correct design and test. In the past, fault tolerance has been generally adopted to electronic systems for many critical mission applications. The possible adoption of fault tolerance techniques for SoCs (to include not only electronics, digital IEEE TRANSACTIONS ON COMPUTERS, VOL. 55, NO. 2, FEBRUARY 2006 97