Abstract
This issue of the IEEE Transactions on Semiconductor Manufacturing contains a special section devoted to papers selected from presentations at the Third InternationalWorkshop on Statistical Metrology, held in Honolulu, Hawaii, on June 7, 1998, in conjunction with the Symposiums on VLSI Technology and Circuits. The papers in this special issue represent a significant effort toward enhancing yield-related metrics and the statistical characterization of processes and circuits, by dealing with several different related aspects of the problem. The topics of the papers include more efficient and accurate statistical simulation algorithms, realistic worst-case modeling of basic integrated system components, automatic top-down propagation of tolerance constraints, a better understanding of the statistical characterization of process uniformity, and the improved modeling of the number of defects seen on wafers.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
