Guest editor's introduction to special section on high-level design validation and test

Abstract

ALIDATION and verification are becoming bottlenecks in designing multimillion-gate systems. Simulation-based and formal-verification-based approaches are being pursued for design validation of such hardware-based systems. Simulation-based approaches such as generation and application of high-level tests, generation and execution of test programs for microprocessors. and hardware-accelerated emulation are finding good use in the industry. Formal-verification techniques such as model-checking and theorem-proving have been used to verify the correctness of small designs. Limited success has been achieved in deploying formal techniques in the context of protocol verification, verification of control logic in (pipelined) microprocessors, and verification of small application-specific systems. Scalability to large-scale industrial designs remains a concern for many verification-based approaches. Recognizing that neither simulation- nor verification-based approaches by themselves can solve the emerging validation problems, the High-Level Design Validation and Test (HLDVT) Workshop was started in 1996 to bring together these two communities. The HLDVT Workshop has successfully focused on addressing practical validation issues, methodologies, and techniques for validation of complex processors and heterogeneous system-on-chips (SoCs) and validation at higher levels of design