Grounding Methods to Reduce Stray Coupling in Multi-Layer Layouts

Abstract

It has been shown that via inductance and associated coupling to neighboring structures in multilayer superconducting integrated circuit layouts is significant when vias pass through ground planes. Via inductance and coupling are also strongly dependent on return current paths. Although ground planes in multilayer layouts are often connected at regular intervals, signal vias can be far from such ground connections. Ground sleeves, where connections between ground planes tightly surround a signal via, consume large layout space in some processes and are thus often avoided. Through numerical and experimental results for test structures, we show how the placement of ground contacts close to signal vias reduce coupling between these vias and other structures in circuits without compromising integration density. We also apply these methods to bias columns in the AIST advanced process layout tiles and evaluate the reduction of coupling from bias lines to circuit structures.