Graphene Nanoribbon Spin Interconnects for Nonlocal Spin-Torque Circuits: Comparison of Performance and Energy Per Bit With CMOS Interconnects

Abstract

Solid-state devices based on utilizing the electron spin for storing and manipulating information may pave the way for next-generation computers. In this paper, the performance and the energy dissipation of graphene spin interconnects in a nonlocal spin-torque (NLST) circuit are compared against those of the CMOS circuit at the end of the silicon technology roadmap (technology year 2020). The interconnect-oriented limitations of the NLST circuit are quantified through exhaustive simulations. The impact of the electron scattering at the edges of the graphene nanoribbon (GNR) on the speed and the energy dissipation of the NLST circuit are evaluated. It is found that, if the edges in the GNR scatter electrons with a 100% probability, then the delay of the interconnect in the NLST circuit is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{10}\times$</tex></formula> higher than its value at perfectly passivated GNR edges for an interconnect with a length of 100 gate pitches and a width of 14 nm. The scattering of electrons at the GNR edges leads to inefficient spin injection in the interconnect, which increases the energy dissipation of the NLST circuit. Energy versus delay landscapes of the NLST circuit and the CMOS circuit are compared. It is found that the energy versus delay of the NLST circuit exhibits a minimum in energy, which is in striking in contrast with the energy-versus-delay behavior of the CMOS circuit.