Abstract

In recent years, on-chip interconnects have been considered as one of the most challenging areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay becomes more pronounced than the gate delay. The continuous scaling of interconnects introduces significant parasitic effects. The resistivity of interconnects increases because of the grain boundary scattering and side wall scattering of electrons. An increased Joule heating and the low current carrying capability of interconnects in a nano-scale dimension make it unreliable for future technology. The devices resistivity and reliability have become more and more serious problems for choosing the best interconnect materials, like Cu, W, and others. Because of its remarkable electrical and its other properties, graphene becomes a reliable candidate for next-generation interconnects. Graphene is the lowest resistivity material with a high current density, large mean free path, and high electron mobility. For practical implementation, narrow width graphene sheet or graphene nanoribbon (GNR) is the most suitable interconnect material. However, the geometric structure changes the electrical property of GNR to a small extent compared to the ideal behavior of graphene film. In the current article, the structural and electrical properties of single and multilayer GNRs are discussed in detail. Also, the fabrication techniques are discussed so as to pattern the graphene nanoribbons for interconnect application and measurement. A circuit modeling of the resistive-inductive-capacitive distributed network for multilayer GNR interconnects is incorporated in the article, and the corresponding simulated results are compared with the measured data. The performance of GNR interconnects is discussed from the view of the resistivity, resistive-capacitive delay, energy delay product, crosstalk effect, stability analysis, and so on. The performance of GNR interconnects is well compared with the conventional interconnects, like Cu, and other futuristic potential materials, like carbon nanotube and doped GNRs, for different technology nodes of the International Technology Roadmap for Semiconductors (ITRS).

Highlights

  • The rapid miniaturization of the transistor feature size in an integrated circuit chip has been observed over the past four decades

  • A systematic study has been carried out to analyze the potential application of graphene nanoribbons (GNRs) as one of the generation of on-chip interconnects

  • Shows semiconducting as well as metallic behavior, depending on the number of dimers, the zigzag edge GNR shows to be always semiconducting in nature

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Summary

Introduction

The rapid miniaturization of the transistor feature size in an integrated circuit chip has been observed over the past four decades. The overall calculations report that the energy gap of the armchair GNR decreases with the increase of the nanoribbon width (w) [5,39]. The CVD-grown and intercalation-doped multilayer-graphene-nanoribbons (MLGNRs) were reported by Jiang et al [28] for their superior interconnect application. Clear optical images were captured showing graphene interconnects on the top layer of the ring oscillator array circuit in CMOS process (Figure 7c,d).

Circuit
10. Schematic
Performance of GNR Interconnects and Comparison with Other Materials
Resistivity
12. Resistance
15. Resistance
Capacitance
16. Capacitance
C L series
Crosstalk Effect
23. Nyquist diagrams diagrams for the the distributed distributed RLC
Findings
Summary and Concluding Remarks
Full Text
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