Abstract
The design and minimization of computer intraconnections have a great influence on system characteristics such as cost, performance, failure rate, and in the case of VLSI, chip area. The problem addressed was the minimization of computer intraconnections with bandwidth and delay constraints imposed. This research problem has been formally defined as a graph theory problem. An heuristic algorithm, H-RASP2, is presented which approximates a minimal solution for this NP-complete problem in polynomial time. H-RASP2 was tested using a variety of graph sizes and fill's. Analysis of the results shows that for the test cases H-RASP2 provides an excellent approximation to a minimal solution.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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