Graph-theoretic algorithm for finding maximal supergates in combinational logic circuits

Abstract

Disjunctive decomposition of a large switching function into several smaller switching functions is an efficient way of solving many problems in logic design and testing areas. Finding disjunctive decomposition of an arbitrary switching function, however, is known to be a very difficult problem for which no practical solutions have been reported. Alternatively, a practical solution is to identify maximal supergates defined by Seth et al. (1985) which represent disjunctive decomposition of a logic circuit which realises a given switching function. An algorithm is presented which identifies maximal supergates in combinational logic circuits. The algorithm is based on both the graph-theoretic algorithms and the set manipulation algorithms such as depth-first search, biconnectivity and UNION/FIND. The time complexity of the algorithm is O(n + e), where n is the number of gates and e is the number of links between gates. Finally, the authors demonstrate experimental results of maximal supergates in ISCAS85 and ISCAS89 benchmark circuits.