Abstract
As a result of the evolution to nano-technology, the demand for accurate Static Timing Analysis (STA) at transistor level for high speed/high performance digital integrated circuits is increased. Despite the existence of many research attempts to resolve the timing analysis problems, (STA) remains the best solution because of the extremely fast run time and accuracy. The accurate modeling for highly resistive interconnects, nonlinear driver and receiver that effects in crosstalk noise analysis require accurate transistor level model. This model provides solution for false paths problem that is found in classic gate or arc models. In this paper, a new graph model is proposed at transistor level to describe the behavior of CMOS circuits. This model is dealing with CMOS circuit as a pool of transistors regardless its positions in the gates to overcome problem of false paths. By this model, accurate circuit timing analysis is estimated based on BSIM4 equations. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested circuits.
Highlights
The revolution from the micro-technology to nano-technology and the growing demand on high performance VLSI chips drive industry companies like Intel and IBM to have their own internal tools
Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates
This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level
Summary
The revolution from the micro-technology to nano-technology and the growing demand on high performance VLSI chips drive industry companies like Intel and IBM to have their own internal tools. The potential slack-time technique [3] was proposed as a very effective metric that measures the combinational circuit performance In this technique, the delay of gates is calculated by using linear equation. In [13], the delay modeling is based on pre-characterization of the effective transition-resistances model Such methods are time and space consuming and incorporate interpolation errors, they are old and don’t accurate for nano-technology parameters because of the development from Micro to Nano dimensions. Clear and explained methods to find the critical time, frequency (CLOCK time), the slack and timing constraints at transistor level are proposed in order to find an effective way for estimating timing analysis of any circuit, and building a tool with clear algorithms and methods for researchers to perform static timing analysis job.
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