Graph-Based Sparsification and Synthesis of Dense Matrices in the Reduction of RLC Circuits

Abstract

The integration of more components into modern integrated circuits (ICs) has led to very large RLC parasitic networks consisting of millions of nodes that have to be simulated in many times or frequencies to verify the proper operation of the chip. Model order reduction (MOR) techniques have been employed routinely to substitute the large-scale parasitic model with a model of lower order with a similar response at the input–output ports. However, established MOR techniques generally result in dense system matrices that render their simulation impractical. To this end, in this article, we propose a methodology for the sparsification of the dense circuit matrices resulting from MOR of general RLC circuits, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. In addition, we describe a procedure for synthesizing the sparsified reduced-order model into an RLC circuit with only positive elements. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy.