GrainFlow: Enable testing for future internet architectures by per-bit customization

Abstract

Programmable routers are key components for building future Internet test beds. Extensive research, such as the OpenFlow project, has been carried out to enhance programmability in the control plane of routers. However, the data plane is inflexible to process arbitrarily-defined packets. Designing a general purpose data plane platform to support distinct networks has been a challenge that must be resolved. In this article, we propose GrainFlow, a fully programmable hardware-based packet processing platform. GrainFlow brings flexibility to data plane by arbitrarily defining operations on every bit of packet, and adapts to variation of packet header length by employing a configurable circular pipeline. We implement GrainFlow on a Field Programmable Gate Array (FPGA) board. Finally, we evaluate the resource utilization and network performance of the GrainFlow architectures presented.