Abstract

Diamond wire sawing has obtained 90% of the single-crystal silicon–based photovoltaic market, mainly for its high production efficiency, high wafer quality, and low tool wear. The diamond wire wear is strongly influenced by the temperatures in the grain-workpiece contact zone; and yet, research studies on experimental investigations and modeling are currently lacking. In this direction, a temperature model is developed for the evaluation of the flash temperatures at the grain tip with respect to the grain penetration depth. An experimental single-grain scratch test setup is designed to validate the model that can emulate the long contact lengths as in the wire sawing process, at high speeds. Furthermore, the influence of brittle and ductile material removal modes on cutting zone temperatures is evaluated.

Highlights

  • In mechanical material removal, the highest share of the input energy is transformed to thermal energy [1]

  • In the case of brittle material removal, as the penetration depth increases, the rate of fracture increases, the energy is dissipated with fracture, and lower temperatures are measured at the grain tip

  • In the ductile material removal case, a higher share of energy is dissipated in the form of thermal energy, leading to a temperature increase as the grain penetration increases

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Summary

Introduction

The highest share of the input energy is transformed to thermal energy [1]. The energy created during the short contact time leads to high temperatures at the grain, called the flash temperatures [4]. The time of contact of a grain with the workpiece is in the range of 1 μs; the interaction can be defined as near-adiabatic. In diamond wire sawing, the presence of long contact lengths emphasizes the influence of temperature effects. Diamond wire sawing is a process predominantly used to slice hard and brittle material into wafers. Wire sawing with fixed grains has evolved to replace wire sawing with slurry due to advantages like lower kerf loss, higher material removal rate, and superior wafer strength [5].

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