Gradual-N-Justification (GNJ) to Reduce False-Positive Hardware Trojan Detection in Gate-Level Netlist

Abstract

The integrated circuit design flow is highly susceptible to hardware Trojan (HT) insertion. While there have been significant efforts to detect HTs, techniques usually demand a golden model, suffer limited scalability, or experience high false positives. This article introduced a new technique called gradual-N-justification (GNJ) to reduce false-positives HT detection in the gate-level netlist. The GNJ technique combines the signal justification and unsupervised K-means machine learning (ML) algorithm. The GNJ technique is a general technique that can be applied to a set of reported suspicious signals (SSs) in order to identify the most SSs and reduce false-positive rates (FPRs) in detecting HTs. The GNJ technique is applied to 60 different combinations of full-scan and partial-scan circuits and hard-to-detect combinational HTs. To realize valid and hard-to-detect HTs, a configurable HT insertion platform is developed. Furthermore, to the best of our knowledge, it is for the first time that an extensive evaluation of partial-scan circuits for HT detection at the gate level is being performed. The comprehensive results on both full- and partial-scan circuits have shown that the GNJ technique is highly scalable as it presents a linear relationship between the number of SSs and the execution time of GNJ. Furthermore, the GNJ technique does not miss an HT circuit if exists. The GNJ technique offers an FPR as low as 3.89% for full-scan circuits and 3.31% for partial-scan circuits on average.