GNLS: a hybrid on-chip communication architecture for SoC designs

Abstract

In this paper, we propose global network local bus (GNLS) communication architecture, where network interface is designed and DMA communication is given. We also study and compare the performance of bus-based and mesh-based with GNLS NoC-based infrastructure by theoretical analysis and simulation. It is shown that NoC-based infrastructure performs better than bus-based one in terms of latency when the number of flits contained in the packets exceeds certain threshold. In addition, GNLS-based infrastructure outperforms mesh-based one under the same condition, which verifies the correctness of the theoretical performance analysis. An example of design is given to show that the proposed architecture has better performance than bus, and Mesh based architecture.