Abstract
A technique to ease the linearity requirement of the input transconductor (Gm) of a Gm-C based continuous-time (CT) Delta-Sigma (ΔΣ) modulator is presented. Compared with RC-based CT ΔΣ modulators, Gm-C-based modulators consume lower power, however they have poorer SNDR due to smaller linear input range. The proposed technique utilizes a single bit quantiser, a 14-tap FIR filter and a compensating Gm cell in the feedback path to cancel the input Gm cell's nonlinearity. System level simulations of a 3rd order modulator demonstrate an improvement of over 30 dB in SFDR with no penalty on the in-band noise floor.
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