Abstract
In this paper, we propose the design of globally asynchronous locally synchronous (GALS) pipelined 16-bit Baugh Wooley multiplier for digital signal processing applications. The primary emphasis of the design is on low power implementation of multiplier. For fair bench marking fully synchronous pipelined 16-bit Baugh Wooley multiplier and GALS pipelined 16-bit Baugh Wooley multiplier are implemented using same FPGA and largely same logic cells. The GALS multiplier is more power efficient; the synchronous multiplier dissipates 3.9 times more power as compared to GALS multiplier. Power efficiency is mainly because of fine partitioning of global clock that simplifies in circuit clock infrastructure and reduce global clock rate.
Published Version
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