Glitch-free design for multi-threshold CMOS NCL circuits

Abstract

In this paper, a novel design is proposed for eliminating glitches and signal bounces during wake-up events that result from incorporating multi-threshold CMOS (MTCMOS) into asynchronous NULL Convention Logic (NCL) circuits. A one-stage 8x8 NCL array multiplier is designed using the proposed method and compared with the previously published paradigm. Evaluation results of glitches, throughput, and power efficiency have shown advantages of the proposed design in all these categories over the state-of-the-art. The effect of supply voltage scaling on the proposed design is also examined and presented.