GLAAPE: Graph Learning Assisted Average Power Estimation for Gate-level Combinational Designs

Abstract

This paper introduces GLAAPE, a novel graph learning-assisted neural network model that enables fast, accurate, and transferable estimation of average power in gate-level combinational designs from Register Transfer Level (RTL) simulation. GLAAPE learns to propagate the average toggle rates by effectively embedding the structural information and logical function feature values as vectors on each logic cell of the netlist file. GLAAPE predicts the output toggle rates of combinational logic cells and hence the average power of the benchmark circuits from inputs obtained through RTL simulation without the requirement of gate-level simulation. We evaluate GLAAPE with the commercial gate-level power estimation tool for inference throughput, which is, on average, 15.69X faster. GLAAPE outperforms the commercial RTL Power estimation tool for average power estimation by achieving a mean improvement of 25.28%. We also compare GLAAPE with the state-of-the-art model GRANNITE to predict the output toggle rates to demonstrate the transferability and achieve better accuracy with a mean improvement of 13.95%. We consider a good range of benchmark circuits for analysis, and our experimental results show the generalization and efficacy capability of GLAAPE.