Abstract
A high-speed programmable counter with a new reloadable D flip-flop which integrates the programmable function to a true-single-phase-clock (TSPC) D flip-flop is presented. The proposed reloadable D flip-flop is able to operate at higher frequencies with lower power consumption compared to the performance of the existing bitcell. The programmable divide-by-N counter implemented with this reloadable D flip-flop using the Chartered 0.18 µm CMOS process is capable of operating up to 2 GHz for a 1.8 V supply voltage with 4.7 mW power consumption.
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