Germanium on Insulator Fabrication for Monolithic 3-D Integration

Abstract

A low temperature ( ${T} _{\max}=350$ °C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm−3 were fabricated. Ge pFETs are fabricated ( ${T} _{\max}=600$ °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of −0.18 V and 60% higher mobility than the SOI pFET reference devices.