Abstract

The performance of strained silicon (Si) as the channel material for today’s metal-oxide-semiconductor field-effect transistors may be reaching a plateau. New channel materials with high carrier mobility are being investigated as alternatives and have the potential to unlock an era of ultra-low-power and high-speed microelectronic devices. Chief among these new materials is germanium (Ge). This work reviews the two major remaining challenges that Ge based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, Ge is compared to compound III-V materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge device architectures, including surface channel and quantum well configurations, are reviewed. Finally, state-of-the-art Ge device results and future prospects are also discussed.

Highlights

  • The motivation to replace strained silicon (Si) with higher mobility channel materials in today’s metal-oxide-semiconductor field-effect transistors (MOSFETs) is well documented [1,2].Saturation drive current (Ion), a critical performance metric for FET devices, is intimately linked with carrier mobility

  • III-V material systems, experimental outcomes have been the inverse of that seen with Ge—i.e., excellent III-V based NMOS devices have been demonstrated [25,26], whereas a comparably performing PMOS device using the same channel material is still elusive to date [1]

  • A good buffer is further characterized by a low threading dislocation density (TDD) and low root-mean-square (RMS) roughness at the surface so that it may serve as a smooth template for active layer growth

Read more

Summary

Introduction

The motivation to replace strained silicon (Si) with higher mobility channel materials in today’s metal-oxide-semiconductor field-effect transistors (MOSFETs) is well documented [1,2]. III-V material systems, experimental outcomes have been the inverse of that seen with Ge—i.e., excellent III-V based NMOS devices have been demonstrated [25,26], whereas a comparably performing PMOS device using the same channel material is still elusive to date [1] This is in large part due to the significant disparity in electron and hole mobility in III-V materials; with μe typically being at least several times larger than μh [1]. For this reason, it is not unlikely that a future CMOS technology node will involve co-integration of Ge based PMOS and III-V based NMOS devices together. This review article presents recent advancements in the field of Ge based nanoscale MOSFETs and QWFETs

Heterogeneous Integration on Silicon
Direct Epitaxy
The Graded Si1–xGex Buffer
The Oxide Buffer
Developing a Suitable Gate Stack
Overview
The GeO2 Passivation Layer
The Si Passivation Layer
Achieving Low-Resistance Ohmic Contacts to n-type Ge
A Comparison
Ge Device Architectures
State-of-the-Art Ge MOSFETs and MOS-QWFETs
Findings
Conclusions and Outlook

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.