Geometry dependent tunnel FET performance - dilemma of electrostatics vs. quantum confinement

Abstract

Tunneling field-effect transistors (TFETs) are attracting a lot of interest because of their potential to reduce power dissipation in logic applications [1–3]. Performance of TFETs is expected to improve with increasing electrostatic control as provided by ultra-thin body (UTB) based single-gate (SG), double-gate (DG), and nanowire based gate-all-around (GAA) structures, respectively (Fig. 1) [4]. Increasing geometrical confinement, however, could also lead to significant quantum confinement effects [4, 5], especially in III–V materials, which is detrimental to TFET performance. A previous study compared the operation of InAs based SG, DG, and GAA TFETs using quantum transport simulations [4]. Because of the use of the tight-binding model for the device structure in [4], however, the important tradeoff between electrostatics vs. quantum confinement in different geometries could not be clearly distinguished. In this work, we use detailed analytical calculations to compare the operation of SG, DG, and GAA TFETs in InAs (Fig. 1), and examine the competing effects of electrostatics vs. quantum confinement. We demonstrate an important tradeoff between the superior electrostatic control vs. current injection efficiency in TFETs with increasing lateral confinement, which will be an essential consideration for future TFET design.