Genetic Algorithms and Artificial Neural Networks to Combinational Circuit Generation on Reconfigurable Hardware

Abstract

Operating in critical environments is an extremely desired feature for fault-tolerant embedded systems. In addition, due to design test and validation complexity of these systems, faster and easier development methods are needed. Evolvable Hardware (EHW) is a development technique that, using reconfigurable hardware, builds systems that reconfiguration part is under the control of an Evolutionary Algorithm. Reconfigurable hardware allows EHW to change its own hardware structure adapting itself to task and/or environment changes. Evolvable part of these systems can also be implemented using Artificial Neural Networks (ANNs). This research work presents results and comparisons between Genetic Algorithm (GA) and ANN implementations that receive combinational circuits' truth-tables as input and searches the minimum circuit respecting this input truth-table. GA improved for this work's EHW structure achieve good execution time for tested tables and ANN modeling presents some non-desired characteristics with bad results.